Aldec Active-HDL 10.1 x64 Active-HDL是集成VHDL,Verilog,EDIF,SystemC开发环境。它由设计工具,VHDl&Verilog编译器,单仿真内核,调试工具,图形仿真和资源、库等管理工具,可让用户运行仿真,综合,实现,以及第三方工具。 Aldec公司所提供的高阶FPGA及ASIC设计和验证环境—Active-HDL,能够协助工程人员进行电信、军事,或者消费性电子等应用的硬体实现。Active-HDL能够和业界标准相容,如IEEE、ISO、IEC及其它标准等,它为您的设计提供了极广的覆盖率及支援。 其它强大的功能和工具,如程式码覆盖率分析(Code Coverage Analysis),图表编辑器,和状态图表编辑器,都能协助您以非平行的方式检视您的设计元素。Active-HDL具备除错工具,能支援Soft或Hard IP Core元件;其它的特色如图形化使用介面、程式语法、或混合模式开发都能加快您的设计速度。 Aldec Active-HDL10.1 (64bit) | 478.7 mb Aldec, Inc.,announces the latest release of its mixed-language FPGA design platform,Active-HDL 10.1. Popular with designers for more than 15 years for FPGA designentry and simulation due to its award-winning and intuitive GUI and highperformance simulator, Active-HDL now offers support for 64-bit simulation tomeet the growing demand of simulation of larger designs.
Active-HDL is an HDL-based FPGA Design and Simulation solution that supportsthe newest FPGA devices available from all leading FPGA vendors. Thehigh-performance, mixed-language solution interfaces with nearly one hundredtwenty (120) third party vendor tools and provides FPGA designers a singleplatform that can be used independently of the targeted FPGA design flow.Active-HDL 10.1 supports design creation and simulation of the newestindustry-leading FPGA devices from Altera, Lattice, Microsemi (Actel),Quicklogic and Xilinx.
More info: https://www.aldec.com/en/fpga_simulation/active-hdl
About Aldec
Established in 1984, Aldec is an industry leader in Electronic DesignVerification and offers a patented technology suite including: RTL Design, RTLSimulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, DesignRule Checking, IP Cores, Requirements Lifecycle Management, DO-254 FunctionalVerification and Military/Aerospace solutions.
Name: Aldec Active-HDL
Version: (64bit) 10.1.3088.5434
Home: www.aldec.com
Interface: english
OS: Windows XP / Vista / Seven / 8 / 8.1
Size: 478.7 mb
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